The disclosure relates to semiconductor integrated circuit devices including area I/O pads laid out in a flip chip having multilayer interconnect layers and power source structures of the flip chip.
To design semiconductor integrated circuits, positions of peripheral I/O regions in which I/O cells are arranged and positions of gate regions in which standard cells or macros are arranged are predetermined. For example, the peripheral I/O regions are peripheral portions of chips serving as semiconductor integrated circuit devices, and the gate regions are center portions (inner portions) surrounded by the peripheral I/O regions. When the semiconductor integrated circuits are designed, the I/O cells, the standard cells, and the macros are designed and arranged in the inner portions of the predetermined peripheral I/O regions and the predetermined gate regions.
FIG. 14 is an overall view illustrating a chip serving as a semiconductor integrated circuit device. In the figure, a chip 200 includes a peripheral I/O region 201 and a gate region 202. Although not illustrated, I/O cells and ESD protection circuits are arranged in the peripheral I/O region 201. As illustrated in the figure, standard cells 203 and macros 204 are arranged in the gate region 202.
Moreover, the I/O cells and the ESD protection circuits are connected to I/O pads each of which is connected to signals input/output to/from the chip 200 or a power source. The I/O pads connected to the power sources are hereinafter referred to as power source I/O pads. The I/O pads connected to the signals are hereinafter referred to as signal I/O pads. When it is not particularly necessary to distinguish the power source I/O pads from the signal I/O pads, they are simply referred to as I/O pads.
Conventionally, the I/O pads are arranged in the peripheral I/O region. In the semiconductor integrated circuit device including such I/O pads, the number of I/O pads increases as the number of signals input/output to/from the chip 200 increases, so that it is necessary to increase the length of chip sides. Here, since the area of the gate region increases as the length of the chip sides increases, there is a concern that dead space in the gate region may increase depending on the gate size. Moreover, when the length of the chip sides increases, the distance from the power source I/O pads arranged in the peripheral I/O region, which is a peripheral portion of the chip, to a center portion of the chip increases. As a result, the resistance value of an interconnect extending from each power source I/O pad to the center portion of the chip increases, thereby increasing the voltage drop. When the voltage drop increases, a voltage supplied to the inner portion of the chip decreases, which may reduce the working speed.
As a technique related to improving the capacity to supply power to the inner portion of the chip, a flip-chip package is used.
With the flip-chip package, the number of signal terminals can be increased, a power source plane can be provided on an intermediate substrate which is referred to as a build-up substrate and connects a package to the chip, and the power source I/O pads can be arranged any positions of the inner portion of the chip, so that it is possible to improve the capacity to supply power to the inner portion of the chip.
FIG. 15 illustrates an example configuration in the vicinity of the I/O pads. FIG. 15 is an enlarged view illustrating a part of the peripheral I/O region 201 of FIG. 14.
A plurality of I/O cells 210 and ESD protection circuits 211 are arranged in the peripheral I/O region 201, which is the peripheral portion of the chip 200. The standard cells and macro cells, which are not shown, are arranged in the gate region 202, which is the inner portion of the chip 200, where the standard cells and the macro cells are in the same layer as the plurality of I/O cells 210.
I/O pads 220a, 220b, 221a, 221b, which are illustrated as squares in FIG. 15 are arranged in a layer different from the layer in which the standard cells and the I/O cells are arranged. When viewed from above, the I/O pads 220a, 220b at least part of which overlaps the peripheral I/O region 201 are referred to as peripheral I/O pads, and the I/O pads which do not overlap the peripheral I/O region 201, that is, the I/O pads 221a, 221b arranged in the gate region 202 are referred to as area I/O pads.
The I/O pads 220a, 221b for digital signals are, as illustrated in the figure, connected to, for example, the standard cells in the gate region 202, which is the inner portion of the chip 200, via the I/O cells 210 and interconnects 230. The I/O pads 220b, 221a for analog signals such as power sources are, as illustrated in the figure, connected to the ESD protection circuits 211, and are connected to, for example, the standard cells in the gate region 202, which is the inner portion of the chip 200, via interconnects 230.
Note that FIG. 15 illustrates an example, and the I/O pads are not necessarily connected to the I/O cells or the ESD protection circuits.
The area I/O pads connected to the power sources are hereinafter referred to as power source area I/O pads, the area I/O pads connected to the signals are hereinafter referred to as signal area I/O pads, the peripheral I/O pads connected to the power sources are hereinafter referred to as power source peripheral I/O pads, and the peripheral I/O pads connected to the signals are hereinafter referred to as signal peripheral I/O pads. When it is not particularly necessary to distinguish these I/O pads from one another, they are simply referred to as area I/O pads, peripheral I/O pads, I/O pads.
Examples of an area I/O pad layout of a flip chip and a power source structure are described, for example, in Japanese Patent Publication No. 2003-068852, Japanese Patent Publication No. 2003-124318, and Japanese Patent Publication No. 2004-047516.
As one of these examples, a conventional area I/O pad layout is illustrated in FIG. 1. A chip 200 of FIG. 1 includes three types of area I/O pads, that is, signal area I/O pads (S symbols in the figure) 102, VDD area I/O pads (V symbols in the figure) 103 serving as power source area I/O pads connected to a predetermined power source VDD, GND area I/O pads (G symbols in the figure) 104 serving as power source area I/O pads connected to a ground power source GND arranged in a region surrounded by a peripheral I/O region 201, that is, in a gate region 202 at an inner portion of the chip 200. The VDD area I/O pads 103 and the GND area I/O pads 104 are included in the power source area I/O pads. The present application describes the arrangement of the power source area I/O pads and the voltage drop, and thus hereinafter only the power source area I/O pads are described.
FIG. 2 is a view focusing on the layout of only the power source area I/O pads 103, 104 of FIG. 1. The layout of FIG. 2 is similar to the area I/O pad layout of Japanese Patent Publication No. 2004-047516. That is, the layout is such that the same power source area I/O pads are aligned in a row direction, and different power source area I/O pads are alternately aligned in a column direction. The VDD area I/O pads 103 or the GND area I/O pads 104 are successively aligned in the row direction, and the VDD area I/O pads 103 and the GND area I/O pads 104 are alternately aligned in the column direction.
FIG. 3 illustrates another layout of power source area I/O pads. In the figure, different power source area I/O pads are alternately aligned both in the row direction and in the column direction. That is, VDD area I/O pads 103 and GND area I/O pads 104 are alternately aligned both in the row direction and in the column direction. This layout is similar to the area I/O pad layout of Japanese Patent Publication No. 2003-124318.
Note that there are several types of semiconductor integrated circuit devices depending on their applications, and examples the types are (1) semiconductor integrated circuit devices provided with peripheral I/O pads but without area I/O pads, (2) semiconductor integrated circuit devices provided with peripheral I/O pads and area I/O pads, and (3) semiconductor integrated circuit devices provided with area I/O pads but without peripheral I/O pads.